A Digital Television Standard published Sep. 16, 1995 by the Advanced Television Systems Committee (ATSC) specifies vestigial sideband (VSB) signals for transmitting digital television (DTV) signals in 6-MHz-bandwidth television channels such as those currently used in over-the-air broadcasting of National Television System Committee (NTSC) analog television signals within the United States. The radio receiver portions of the HDTV receiver used by the Advanced Television Systems Committee (ATSC) for field testing of the standard were designed by Zenith Electronics Corporation. In the Zenith receiver, phase tracking is done at baseband after synchronous detection is done. Digitization is done after synchronous detection. The digital transmission scheme authorized by the ATSC is unusual because it uses vestigial-sideband amplitude modulation (VSB AM).
In U.S. Pat. No. 5,479,449 entitled "DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER, AS FOR INCLUSION IN AN HDTV RECEIVER", which issued Dec. 26, 1995 to C. B. Patel and A. L. R. Limberg, digitization is done before synchronous detection; and phase tracking is done at intermediate frequencies before generating complex-number digital samples for synchronous detection. U.S. Pat. No. 5,479,449 teaches that, despite lack of symmetry of VSB AM upper and lower sidebands, phase tracking can be done at intermediate frequencies before generating complex-number digital samples for synchronous detection in VSB AM receivers. Narrow bandpass filtering is done to achieve symmetry of upper and lower sidebands before extracting carrier to be synchrodyned to baseband to develop control signal for the bandpass tracker. Alternatively, the carrier is extracted from the asymmetrical upper and lower sidebands, synchrodyned to baseband and lowpass filtered to develop control signal for the bandpass tracker, the cut-off frequency of the lowpass filter being so low in frequency that there is no response to the asymmetrical portion of the carrier sideband structure.
Bandpass phase trackers are also useful for detecting digital television signals transmitted by QAM of a center-channel carrier as described in U.S. Pat. No. 5,506,636 entitled "HDTV SIGNAL RECEIVER WITH IMAGINARY-SAMPLE-PRESENCE DETECTOR FOR QAM/VSB MODE SELECTION", which issued Apr. 9, 1996 to C. B. Patel and A. L. R. Limberg, and in allowed U.S. patent application Ser. No. 08/266,753 entitled "RADIO RECEIVER FOR RECEIVING BOTH VSB AND QAM DIGITAL HDTV SIGNALS", which was filed Jun. 28, 1994 for C. B. Patel and A. L. R. Limberg.
U.S. Pat. No. 5,479,449 digitizes the sidebands of the in-phase synchronous detection result after converting the real samples to complex samples using a digital filter with Hilbert transform system function for generating the imaginary samples. This Hilbert transformation is done by digital filtering of intermediate-frequency (IF) signals with system functions between one and ten MHz in frequency, which is considerably simpler to do than performing the Hilbert transformation at baseband. The delay required to achieve a 90.degree. phase shift at a megahertz is considerably less than that required to approximate 90.degree. phase shift at close to zero frequency. Nonetheless, the Hilbert transformation filter circuitry involves a substantial amount of digital hardware one would prefer to avoid having to use.
C. B. Patel and A. L. R. Limberg considered replacing the Hilbert transformation filter circuitry with differential 90.degree. phase shift networks using FIR or IIR digital filters. U.S. Pat. No. 5,548,617 issued Aug. 20, 1996 and entitled "DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING
RADER FILTERS, AS FOR USE IN AN HDTV RECEIVER" describes differential 90.degree. phase shift networks using IIR digital filters based on a type described by C. M. Rader in his article "A Simple Method for Sampling In-Phase and Quadrature Components", IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS, Vol. AES-20, No. 6 (November 1984), pp. 821-824. In U.S. Pat. No. 5,731,848 issued Mar. 24, 1998 to C. B. Patel and A. L. R. Limberg, and entitled "DIGITAL VSB DETECTOR WITH BANDPASS PHASE TRACKER USING NG FILTERS, AS FOR USE IN AN HDTV RECEIVER" C. B. Patel and A. L. R. Limberg describe differential 90.degree. phase shift networks using FIR digital filters based on types generally described by T. F. S. Ng in United Kingdom patent application 2 244 410 A published Nov. 27, 1991 and entitled "QUADRATURE DEMODULATOR".
The Hilbert transformation filter circuitry is implemented as a digital filter in the bandpass trackers described above after analog-to-digital conversion is performed by a single analog-to-digital converter (ADC) operative on the penultimate intermediate-frequency signal used in the receiver. This penultimate IF signal is located in the very high frequency (VHF) band somewhat below television broadcast channel two. A DTV receiver using a bandpass tracker usually will be designed as a triple-conversion receiver, converting radio-frequency (RF) signals as received from an antenna or cable connection to a first intermediate-frequency signal located in the ultra-high frequency (UHF) band somewhat above television broadcast channel eighty-three, converting amplified UHF first IF signal to the VHF penultimate IF signal, and finally converting amplified VHF penultimate IF signal to an ultimate IF signal somewhere within about a 1-10 MHz frequency range, for synchrodyning to baseband. Using a single ADC in a digital communications receiver avoids any problem of matching separate ADCs respectively used for converting a real component and an imaginary component of analog ultimate IF signal, as well as any problem of matching the gains of the real and imaginary components respectively supplied to these ADCs. Also, the problem of developing real and imaginary components of the ultimate IF signal that are in accurate 90.degree. phasing is largely avoided.
Further, the practice when digitizing signals in a digital communications receiver has been to use a flash analog-to-digital converter, and the high 10.76 megasymbols per second symbol rate and eight- or sixteen-level symbols used in DTV signals impose very difficult operating demands on a flash converter. A flash converter has a considerable amount of circuitry for incorporation within a monolithic integrated circuit (IC) die, employing a (2.sup.n -1)-resistor ladder voltage divider and (2.sup.n -1) comparators to achieve n-bit digital resolution, n being a positive integer. Considerable area is taken up on the die, so ADC cost is quite high, in the several dollar range. A flash converter consumes considerable power for operating at at least 21.52 million samples per second rate as required in the receiver for digitizing VSB AM DTV signals with 10.76 million symbols per second, when a bandpass phase tracker is used. The desire to use as few expensive, power-consuming IC devices as possible directs one skilled in the art away from considering the use of plural-phase analog-to-digital conversion.
In order to get digital resolution of ten to twelve bits at 21.52 million samples per second rate, in order better to facilitate equalization filtering, the inventor has considered the use of analog-to-digital conversion methods other than flash conversion. The inventor discerns that a single flash converter can be replaced by twenty-four ADCs of successive binary approximation type arranged for staggered sampling to provide 24-phase analog-to-digital conversion with up to eleven or twelve bits resolution without need for successive binary approximation rates above DTV symbol rate. Each ADC digitizes a sample of one-half symbol period duration. Conversion rate of each ADC is one-twenty-fourth that of the flash converter, which tends to reduce power consumption by the square of twenty-four in each ADC with an overall reduction of power consumption by a factor of twenty-four. Each ADC of successive binary approximation type has only one to twelve comparators therein depending on the specific type of ADC being used, this being fewer than the (2.sup.9 -1) to (2.sup.12 -1) comparators used in a flash converter with 9-bit to 12-bit resolution and never appreciably more than the (2.sup.8 -1) comparators used in a flash converter with 8-bit resolution.
The ATSC Digital Television Standard published Sep. 16, 1995 specifies symbol coding of trellis coded signals. Twelve time-interleaved trellis codes are used for data within 828-symbol data segments, each data segment being preceded by a 4-symbol data synchronization code group as a header. The original purpose of using twelve time-interleaved trellis codes was to facilitate comb filtering to suppress artifacts of co-channel interfering NTSC signal. In the Zenith receiver used for field testing the ATSC Digital Television Standard, the twelve time-interleaved trellis codes are decoded on a 12-phase basis, using a respective trellis decoder for each of the twelve phases of trellis decoding. Each trellis decoder can use a "soft decision" technique of the type described by Viterbi, which decision procedure is substantially independent of the decision procedures in the other trellis decoders. The use of independent time-interleaved trellis codes reduces the concern in regard to matching the conversion gains of the ADCs exactly, when using the 24-phase analog-to-digital conversion procedure described above. Unless ghosting is substantial, so the equalization filtering commingles ADC responses considerably, differences in the conversion gains of the ADCs are compensated for in some part by the individual "soft decision" procedures in the trellis decoders.
If ADC matching can be done satisfactorily in any case, plural-phase conversion with fewer phases, such as sixteen, should be feasible. This would reduce the amount of hardware required in the complete analog-to-digital conversion circuitry. The possibility of analog-to-digital conversion circuitry capable of providing digital resolution of ten to twelve bits at 21.52 million samples per second rate without as much power consumption or as much device cost encouraged the inventor to consider how the problems of separate analog-to-digital conversion of the real and imaginary components of the ultimate IF signal can be overcome, rather than avoided.
The problem of equalizing gains for the real and imaginary components of the ultimate IF signal as presented in analog form to their respective ADCs is capable of satisfactory solution by supplying the penultimate IF signal to a pair of switching-type mixers that are of matched construction, which switching-type mixers are switched in response to in-phase and quadrature-phase output signals of a penultimate local oscillator. The pair of switching-type mixers that are of matched construction are, for example, formed in a monolithic IC using a tree of emitter-coupled bipolar transistor pairs. The switching-type mixer responses are similarly lowpass filtered to generate respective input signals for the two ADCs. Respective LC lowpass filters designed to be driven from effectively zero source impedances are recommended for maintaining equal insertion gains for the real and imaginary components of the ultimate IF signal as presented in analog form to their respective ADCs.
The problem of developing real and imaginary components of the ultimate IF signal that are in accurate 90.degree. phasing is solved in such an arrangement by supplying the in-phase and quadrature-phase output signals of the penultimate local oscillator in accurate phasing. This simplifies the problem since the penultimate local oscillator output signals are essentially free of modulation.
The problem of matching ADC characteristics is capable of solution, for example, by using matched constructions within a single monolithic IC. If the ADCs are flash converters, they are preferably arranged to use one resistor ladder in common. If the ADCs are of successive binary approximation type, they are preferably arranged to use the same network for establishing the comparator standards used in the successive approximation procedures.